High data reliability, high speed of memory access, reduced chip size, and reduced power consumption are features that are demanded from semiconductor memory.
In recent years, there has been an effort to reduce power consumption by providing input signals having with reduced voltages. The reduced voltages indeed reduce power consumption. However, the reduced voltages may cause voltage sensitivity issues in an input buffer. For example, the input buffer may have an offset voltage (Voff) that is a gap between a reference voltage (VREF) that is provided to determine an inversion point (Vx=the voltage of an input node corresponding to a transition of a voltage at an output node from a logic low level “L” to a logic high level “H”) between a logic high level and a logic low level of an input signal and a threshold voltage used in the input buffer responsive to the reference voltage (VREF). Offset voltages (Voff) of input buffers may slightly vary the inversion point (Vx) from device to device, and the reduced small voltage amplitudes have small tolerances for the small offset voltages that introduce undesired errors in determining the inversion point based on the reference voltage (VREF) voltage as designed.
In order to alleviate the effect of the offset voltage (Voff) of each input buffer to a preferable level, an offset voltage Voff adjustment circuit including a test input buffer and a main input buffer having the offset voltage (Voff), may be provided. FIG. 1A is a schematic diagram of an offset voltage (Voff) adjustment circuit in a semiconductor device in a normal mode, including an input pad, a test input buffer and a main input buffer. FIG. 1B is a schematic diagram of the offset voltage (Voff) adjustment circuit in the semiconductor device in a test mode, which reduces the offset voltage (Voff) and thus makes Vx closer to VREF.
The offset (Voff) adjustment circuit may include the test input buffer for testing. For example, the test input buffer may be an input buffer that receives an input signal from an input pad. For example, the input signal may have a suitable voltage for complementary metal-oxide semiconductor (CMOS) devices. For example, the test input buffer may include a logic AND gate.
The offset (Voff) adjustment circuit may include a switch SW1 between an input pad, the test input buffer and the main input buffer. The switch SW1 switches between an input node of the main input buffer and an input node of the test input buffer, and thus the switch SW1 couples the input pad to one of the input node of the main input buffer and the input node of the test input buffer. For example, a pass gate may be used as the switch SW1. The offset (Voff) adjustment circuit may include a switch SW2 between a reference node having a reference voltage (VREF) and the input node of the main input buffer. When the switch SW2 is turned on (e.g., closed), the switch SW2 couples a reference voltage generator to the input node of the main input buffer, and the reference voltage (VREF) may be provided to the input node of the main input buffer.
The offset (Voff) adjustment circuit may include the main input buffer that has the input node and a reference input node coupled to the reference node having the reference voltage (VREF). The main input buffer detects a relative voltage of an input voltage at the input node to the reference voltage (VREF) and determines an output voltage of an output signal. For example, the main input buffer may provide the output signal at a logic high level when the relative voltage is positive, which means that the input voltage is higher than the reference voltage (VREF). The main input buffer may provide the output signal at a logic low level, if the relative voltage is negative, which means that the input voltage is lower than the reference voltage (VREF). For example, the main input buffer may include a comparator circuit.
In the normal mode, for example, the switch SW1 couples the input pad to the input node of the main input buffer, as shown in FIG. 1A. Thus, the input voltage (VIN) of the input signal may be provided to the input node of the main input buffer when the switch SW1 is turned on. The switch SW2 is not turned on and is open. FIG. 2 is a graph-based diagram showing relationships between an output level of a main input buffer and a combination of the input voltage (VIN) and the reference voltage (VREF). As shown in FIG. 2 of “Output Level (Ideal)” and previously described, the main input buffer is designed to provide the output signal at a logic low level (“L”) when the input voltage (VIN) is lower than the reference voltage (VREF). The main input buffer is designed to provide the output signal at a logic high level (“H”) when the input voltage (VIN) is higher than the reference voltage (VREF). In this situation, Voff=0 and Vx=VREF. This is an ideal case, however, an offset voltage (Voff) of an actual input buffer tends to be non-zero, thus the inversion point Vx differs from the reference voltage (VREF). To adjust this error, a test mode has been used.
In the test mode, the switch SW1 couples the input pad to the test input buffer and the switch SW2 couples the reference node to the input node of the main input buffer, as shown in FIG. 1B. Thus, the reference voltage (VREF) is provided to the input node of the main input buffer. The main input buffer has an offset voltage (Voff) adjustment functionality for adjusting the offset voltage (Voff) based on a test signal (e.g., Voff adjust control flags TVxAdj). For example, the test signals, such as Voff adjust control flags TVxAdj, may take eight different values from 0 to 7, however, the values may not be limited to the range from 0 to 7. The main input buffer may change a level of the output signal responsive to the test signals. For example, an input buffer as shown in FIG. 2, may have an inversion point (Vx) to determine whether the main input buffer may provide the output signal having a logic high level (“H”) or a logic low level (“L”) that becomes lower than the reference voltage (VREF) as designed, responsive to the Voff adjust control flags TVxAdj representing a value that is equal to or less than “2”. On the other hand, the input buffer as shown in FIG. 2 may have the inversion point (Vx) that becomes higher than the reference voltage (VREF) as designed, responsive to the Voff adjust control flags TVxAdj having a value that is equal to or greater than “3”. A tester (not shown) may monitor the logic level of the output signal of the main input buffer in the test mode, and may further determines that the Voff adjust control flags TVxAdj having a value “2” may be used for Voff adjustment of the main input buffer. Because the offset voltages of input buffers may vary due to variations of MOS devices, the appropriate value of the Voff adjust control flags TVxAdj varies from input buffer to input buffer. The tester may set an appropriate value of the Voff adjust control flags TVxAdj, using a fuse in the semiconductor device including the input buffers, in order to adjust an offset voltage Voff for each input buffer. For example, the tester may be located outside of the semiconductor device.
In the above Voff adjustment circuit, the switch SW1 is coupled to the input pad and the main input buffer in series. Typically, the switch SW1 including MOS devices causes impedance in the Voff adjustment circuit between the input pad and the main input buffer. The impedance in the Voff adjustment circuit lowers an operational speed of the semiconductor device. Thus, a Voff adjustment circuit without the switch SW1 between the input pad and the main input buffer is desirable.